1. Field of the Invention
The present invention relates generally to the field of microprocessor memory systems, and more particularly to a system that supports a multiple width memory subsystem.
2. Discussion of Related Art
A typical computer-based processor system (or computer system) consists of three major subsystems: a main memory, one or more central processing units (CPU) and an input-output (I/O) subsystem. In a computer system, the various subsystems must have interfaces to one another. For example, the memory and CPU need to communicate, as well as the CPU and I/O devices.
This communication is typically done via a bus. The bus serves as a shared communication link between the subsystems. Two major advantages of having a bus are low cost and versatility. By defining a single interconnection scheme, new devices and subsystems can easily be added to the computer system. Moreover, peripherals may even be ported between separate computer systems that use a common bus.
One reason bus design is so difficult is that the maximum bus speed is largely limited by physical factors: the length of the bus and the number of devices (and, hence, bus loading). These physical limits prevent arbitrary bus speedup.
The objective of designing a memory subsystem is to attempt to match processor speed with the rate of information (or bandwidth) of memory at the lowest level and most reasonable cost. For main memory, we can use a wider bus called a "memory bus" to increase the memory bandwidth or to reduce the latency of memory. In the case of a memory subsystem, the memory bandwidth is the number of memory bytes that can be transferred (either fetched or stored) between the CPU and the memory per unit time. Hence, the maximum memory bus bandwidth B is equal to B=W/Tm byte/s, where W is the width of word in bytes delivered per memory cycle Tm.
Oftentimes, a variety of different size memory buses are available to help increase performance. However, designing a system that allows access to multiple external buses having different widths presents a design problem. If, for example, a system that is currently configured to accept data from the memory bus in 32 bit blocks, a 64 bit data transfer will create a predicament for the CPU and/or cache. Consequently, a system is needed that allows memory buses with different widths to be utilized without changing the overall configuration of the computer system. For a more in depth discussion of the above, see Hennessy et al., Computer Architecture a Quantitative Approach, Morgan Kaufmann Publishers (1990).